Forum Discussion

NGord's avatar
NGord
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

get_pins

I notice that derive_pll_clocks produces a souce name in my design of -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}]. However the node name "q_sys_inst|enet_pll|sd1|pll7|inclk[0]" ...
Configuration
  • NGord's avatar
    NGord
    2 years ago

    I think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.

ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


Do you have any further concern or consideration on this thread?


Thanks,

Best Regards,

Sheng


NGord's avatar
NGord
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

derive only works for PLLs
Name finder doesnt obviously indicate the source fro a clock which is generated out of a mux or logic.
Any other suggestions such as using the keep attribute in the RTL?

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    That's what the clocks report is for. Identify what pins/ports the tool thinks are clocks and create clock constraints for them. If it's a clock that you are generating yourself, then you should know what the source should be and include it in the create_generated_clock command.

    For a simple example, if you create a divide-by-two clock with a register and a feedback inverter, the clock target is the Q output of the register and the source is the D input.

    • NGord's avatar
      NGord
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      I think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.