Forum Discussion
NGord
Occasional Contributor
Occasional Contributorget_pins
I notice that derive_pll_clocks produces a souce name in my design of -source [get_pins {q_sys_inst|enet_pll|sd1|pll7|inclk[0]}]. However the node name "q_sys_inst|enet_pll|sd1|pll7|inclk[0]" ...
I think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.
sstrell
Super Contributor
Super Contributorderive_ commands make it easy to create SDC for internal nodes of IP that you don't ever need to reference. For your own logic, just use the Name Finder accessed from any of the GUI dialog boxes you can use from the text editor to add SDC. And you don't have to use derive_pll_clocks if you don't want to (though you should). The -source could just as easily be the input clock pin to the PLL, easily found with the Name Finder..
