Occasional ContributorI think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.
Occasional Contributorderive only works for PLLs
Name finder doesnt obviously indicate the source fro a clock which is generated out of a mux or logic.
Any other suggestions such as using the keep attribute in the RTL?
Super ContributorThat's what the clocks report is for. Identify what pins/ports the tool thinks are clocks and create clock constraints for them. If it's a clock that you are generating yourself, then you should know what the source should be and include it in the create_generated_clock command.
For a simple example, if you create a divide-by-two clock with a register and a feedback inverter, the clock target is the Q output of the register and the source is the D input.
Occasional ContributorI think if you use the Keep attribute within the source code then you can use the Verilog/VHDL netnames in the sdc file. Seems to work anyhow.
