General questions from a first time user...

Well, for a start, with a different board the pinout is going to be different, and the available peripherals may be different.

I understand it then, that there's a bit more to just compiling the software for the other board. It seems like I would not only have to compile the software, but also look through the pin assignments. I guess I would also have to specify where the software is to find the ram and VGA port, and opposed to where the software was written to find the peripherals. I should mention that I was able to successfully go through Grant Searle's Multicomp project and build the project with external ram, VGA and ps/2 ports on the mini board. I was hoping this might be somewhat of a straight forward process, but it looks like I may need to take a few steps back, get a few tutorials under my belt, and then try to understand how to port a project. Thank you for the reply.

If you are talking about compiling VHDL/Verilog, this is NOT software. This is hardware description language. It builds firmware for the fpga. Software is what you might run on your Z80 that exists inside an FPGA.

I wrote a simple top-level design for the DE1 and posted it in this thread:

Hi Dave,

Hi,

Terasic DE1 'basic' example
---------------------------
4/25/2012 D. W. Hawkins (dwh@ovro.caltech.edu)
Terasic DE1 Cyclone II FPGA kit 'basic' design.
Counters are used to blink or generate counts using the three
onboard clock sources as follows;
 * KEY is used as the reset input
 * KEY drive the 3 MSBs of the red LEDs
 * 7 switches connected to 7 of the 10 red LEDs.
 * 8 green LEDs blinked using the 24MHz clock
 * Hexadecimal displays A and B count based on the 27MHz clock
 * Hexadecimal displays C and D count based on the 50MHz clock
The design can be synthesized as follows;
1. Unzip the example design into 
   c:/temp/de1_basic
   
   when using windows to unzip the file, unzip
   de1_basic.zip into c:/temp and the folder
   c:/temp/de1_basic will be created.
2. Start Quartus II.
3. Click in the Tcl console.
   If the Tcl console is not visible, bring it up
   using View->Utility Windows->Tcl console
   
4. Use the Tcl console to change to the directory to
   the de1_basic/ folder, eg., at the Tcl console type
   tcl> cd {c:\temp\de1_basic}
   
   Where 'tcl>' is the console prompt.
   
   The parathases {} pass the Windows format directory
   to Tcl as a list variable. This allows you to copy
   and paste the directory path from Windows Explorer.
   
5. Run (source) the synthesis script
   tcl> source scripts/synth.tcl
   
   The Tcl console will then output the build sequence:
     Synthesizing the DE1 'basic' design
     -----------------------------------
      - Quartus Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
      - Creating the Quartus work directory
        * C:/Temp/de1_basic/qwork
      - Create the project 'de1'
        * create a new de1 project
      - Creating the VHDL files list
      - Applying constraints
      - Processing the design
      - Processing completed
6. Download the design
   Plug in the DE1 USB-Blaster and download the .sof file.
   The LEDs and hex displays should start to blink/count.
   Read the comments in src/de1.vhd for details on the basic design.
Enjoy!
Cheers,
Dave
7/12/2014: Checked synthesis with Quartus 13.0sp1.
           Updated the readme.txt. No code changes.

On to your other questions ...