General questions about memories, configuration and FPGA systems.

Hi,

I have done some research on the forum about the topic, but i have still some questions and want

to verify and sum up everything. In my questions about system configuration i will refer to Cyclone III

device family.

1. Some memories questions:

1a. Regarding SRAM memory for NIOS II code. I have seen people using two chips with 16 buses in

parallel giving 32 bit bus. I haven't verified that, but is NIOS II using 32 bit instructions ? So it would be

most efficent to use it like that. What about using only one chip ? Does it mean that NIOS would have

to read the memory two times - so the code could be executed slower ?

Also on this forum couple of people suggested for that not using A0 of the SRAM chip address.

I was looking for SRAM chips on digikey with 32 bit data bus already - they are quite expensive.

That's why it is better to use two 16 bit chips?

1.b. Is external SRAM memory with 10ns access time really much slower that for example internal

on-chip sram with 100 MHz clock?

1c. Regarding FLASH memory. There are two main types of flash NANDs and NORs. As farest i know

NAND have to be read/written in a page manner, while NORs can be accessed directly at desired

address. Is it always better to use NORs with FPGA? Or is there a purpose for using NANDs?

1d. What about the main difference between SRAM and DRAM ICs. I know that:

- SRAM usually has 6 transistors, and DRAM is one MOSFET + capacitor - so it's cheaper.

- SRAM doesn't have to be constantly refreshed so it consumes less power.

- And last thing that - please correct me if i'm wrong: SRAMs are faster, that's why they used as a

cache memory, but ultimately DRAM synchronous clock, bursts allow for higher bandwidth ?

1e.Is with those other memories the same consideration about NIOS 32 bit bus and instructions?

2. System configuration.

I have found out that EPCS configuration memories are quite expensive, that's why people usually

don't use them, right ?

Let's stick for a while with that memory anyway.

2a. I have read Cyclone III documentation regarding configuration. Active Serial is used with EPCS

chips. I read the remote configuration part, and it seems that i can store as many configuration files in

the epcs as i want. If the time comes i can using NIOS or my custom logic to reconfigure FPGA with

a different code, configuration. The documentation suggested that the address for the memory

configuration to start with is at the beginning of the EPCS.

"When used with configuration memory, remote update mode allows an application

configuration to start at any flash sector boundary."

Is that correct ?

2b. In the same documentation there was also smth about that configuration memory can mean not

only EPCS device but also parallel flash memory.

Does it mean that for example instead of using expensive EPCS i could use cheaper NOR flash or

what kind of flash ? and that i could have the same functionality, with remote configuration etc. using

Active Serial?

Ok just right now i have found here

http://www.altera.com/support/devices/configuration/cfg-compare.html

that it can be used, and it's called AP. And that it needs CFI flash.

Any traps here?

2c. Can i in the same CFI Flash memory hold both more conifguration files and the code for NIOS II ?

There are some NIos commands like:

sof2flash, elf2flash, nios2-configure-sof,nios2-flash-programmer. Using those commands i can put

everything that i want in that flash in different address space?

It simply needs the pinout for FLASH and it knows how to use it?

I can use for the connection FPGA GPIO?

2.d In case of having nios code in the same FLASH, i should simply give NIOS the addres of the

beginning of the code for it in FLASH as a Reset Vector.

2.e. I haven't found that out - how is the code then copied to run from SRAM (for faster execution) -

Because i can assume that it could be run directly from that flash.

2.f. Before i started to write this post i was thinking about using some microprocessor to program the

FPGA using PS or FPP. I wanted to use some FLASH memory to store all different configurations for

the FPGA, and mircoprocessor would simply read the FLASH and program the FPGA.

I could use UART, USB or any different protocol i can come up with to upgrade for example the FPGA configuration

automatically.

However FPGA can receive data, reprogram the CFI Flash and reconfigure itself.

So correct me if i'm wrong but there is really no need for external uC?

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Thanks for any answers to my questions, please address them by points and feel free to write some

other stuff that i should consider, read documentation etc.

best regards,

madness