General questions about memories, configuration and FPGA systems.

Yes, a 32 bit read/write from a 16 bit memory will take 2 cycles. That's pretty much a given.

But even if the instruction only wants to read 8 or 16 bits, NIOS will perform read 32 bits, using two 16 bit accesses to the memory controller.

And even if the instruction only wants to write 8 or 16 bits, there'll be two 16 bit accesses to the memory controller, with the byte enables being used to only write the intended address.

That's the extra inefficiency.