General questions about memories, configuration and FPGA systems.

The 16bit read will take an extra cycle (I think it is only 1, but it might be more - I avoid the bus width adapters if possible).

The nios cpu always stalls while doing an avalon cycle, the minimum delay is 2 clocks - so the instruction takes 3 clocks + any 'late result' stalls if the value read is used in the following 2 instructions. Reads from off-chip memory will be significantly slower (writes can be 'posted' and complete in later clocks).

The Nios cpu itself doesn't have an option to 'post' Avalon writes.

Accesses to tightly coupled data memory do not stall - except for a single clock stall for a write immediately following a read to the same tightly coupled memory block.