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It is also worth pointing out that all read cycles done by the nios cpu assert all 4 byte enables, the unwanted bytes are discarded internally.
Write cycles will assert the 'correct' byte enables. However if a byte write is done to an 8-bit slave the 'fabric' will always generate 4 write cycles - 3 of which will have the (single) byte enable inactive.
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Hi Dsl,
I don't really understand those memory byte enables.
If i wanted to use memory with 16-bits i could really simply tie those to correct values and never use them again ?
If i wanted to use the memory with 8-bit data i could use those byte enables to:
1. Select the lower byte - write the data at address 0
2. Select the higher byte - tie the data at address 0
3. Select the lower byte - write the data at address 1
4. Select the higher byte - tie the data at address 1
So it would effectively change the memory organization. But those byte enables are only masks, as i suppose they are only for the reason to not
change the higher/lower word when connecting with 16-bit data line.
Are normal memory controllers for 8-bit 'fabric' chips as you say, able to use effectively
16-bit memory ? Because those byte enables are only for masking data. When connecting 8 bits to D[0..7] of memory i'm able to
write only to lower bytes. Those bytes enables normally are not for routing the data internally in memory chip. So when connecting to 8-bit to 16-bit memory those bytes enables really doesn't matter, right?
Are there any other usage for byte enables? The same concept would be in DDR memories?
best regards,
madness
Honored Contributor
