Gates are not appeared in RTL viewer

Hey all,

I wrote the next code:

module increase_duration_1(in, clk, out, reset);

parameter LEN=10;

input in,clk, reset;

output out;

wire [LEN-1:0] or_out,path;

wire rstn;

or U2(or_out[0],path[0],path[1]);

assign out=path[LEN-1];

assign path[0]=in;

not not1(rstn,reset);

genvar i;

generate

for (i=0; i<LEN-1;i=i+1)

begin: shift_reg

dff u( .clk(clk),

.d(path),

.q(path[i+1]),

.clrn(rstn),

.prn(1'b1));

end

endgenerate

generate

for (i=1; i<len-1;i=i+1)

begin: or_connections

or u3 (or_out,or_out[i-1],path[i+1]);

end

endgenerate

endmodule

attached photo shows what I get in RTL viewer. why I don't see logic gates?

what am I doing wrong?

Thanks in advance