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Altera_Forum
Honored Contributor
Honored ContributorGates are not appeared in RTL viewer
Hey all, I wrote the next code: module increase_duration_1(in, clk, out, reset); parameter LEN=10; input in,clk, reset; output out; wire [LEN-1:0] or_out,path; wire rstn; or ...
Altera_ForumHonored Contributor
Honored ContributorThe or gates are ignored, because they don't generate any output signal in your design.
