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Altera_Forum
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14 years ago

Gates are not appeared in RTL viewer

Hey all, I wrote the next code: module increase_duration_1(in, clk, out, reset); parameter LEN=10; input in,clk, reset; output out; wire [LEN-1:0] or_out,path; wire rstn; or ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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What is about the NOT gate.

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Look sharp, it has been simply absorbed by inverting the signal. But this doesn't mean much, because RTL is just a functional circuit. You have to review the synthesiszed netlist to see how the cicruit is implemented in LEs.