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Thanks for the reply rbugalho. How would you go about fixing the timing violations?
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The short answer is that you make sure that the inputs to your design meet the input setup and hold timing constraints. See next reply for more
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I also don't understand what you mean by constraints. I've never used the timing simulations before. Could you please give me a little understanding as to what you mean?
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Take a look at the timing report. Let's say that it says that signal 'a' has a setup time requirement of 10 ns before the rising edge of 'clk' and a hold time requirement of 2 ns after the rising edge of 'clk' (this is a completely fabricated example, meant to demonstrate the principle not necessarily what you're actually seeing).
Now, in your testbench let's say you have the following for signal 'a'.
process(clk)
begin
if rising_edge(clk) then
a <= ...
end if;
end process;
The signal 'a' will transition 1 simulation delta cycle after the rising edge of 'clk' (one simulation delta cycle is essentially equivalent to 0 ns). If you did that, then 'a' would not meet the hold time of 2 ns specified in the timing report.
Now let's modify the example a bit to 'fix' the hold time problem by adding a 9 ns delay; let's also assume that 'clk' has a period of 10 ns.
clk <= not(clk) after 5 ns; -- This will generate a 10 ns period clock
process(clk)
begin
if rising_edge(clk) then
a <= ... after 9 ns; -- Delaying 'a' to fix the hold time problem
end if;
end process;
Now the problem is that 'a' will transition 9 ns after the rising edge of 'clk' which is the same thing as 1 ns before the rising edge of 'clk'. This will violate the setup time requirement specified in the timing report.
The end result of the story is that the testbench inputs must meet the timing requirements listed in the FPGA's timing report.
There is a analogous story to be told on the output side. If the timing lists that some output 'b' is valid 5 ns after the rising edge of the clock, then you would not want to flag it as a problem right at the rising edge or 1 ns after; you would need to wait until 5 ns after.
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Also, I specified a clock as fclk in my testbench, and used it in some of my always statements. Is that the same as specifying a clock? If not, then how do I specify it.
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Assuming that what you're saying here is that you specified a clock frequency of (example) 100 MHz, and then the testbench generates a 10 ns clock then yes you're correct.
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I know these questions are pretty basic, but this is my first time perfoming a gate level simulation, and any suggestions would be greatly appreciated.
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If you understand how to generate the timing constraints for the tool to use during synthesis then you would likely understand how to generate the testbench. Since you're asking the question, I'm guessing that the input constraints weren't setup properly. The first clue to this is if you do not understand what the timing requirement
output report is telling you.
For example, if signal 'a' has a setup timing requirement of 15 ns relative to 'clk', is that good? Well, the answer is whether or not you specified a desired requirement and how it compares to 15 ns. If your analysis says that the PCBA will produce something that allows for 20 ns of setup time you're good; if it says 10 ns then it will (eventually) fail. You don't need to do this manually; the idea is that you
- Perform analysis to determine what the requirements are for the FPGA design
- Enter the results of that analysis into Quartus (aka 'constrain' the design)
- Run Quartus
- Inspect Quartus' timing report to see if it reports any requirements that could not be met (aka 'fails timing').
The short answer (if you can call this short) to your question about the testbench is that the testbench must match reality in some sense (i.e. nothing transitions 0 ns after 'clk''). The long answer is that maybe you need to get up to speed on how to perform static timing analysis. It's not quite clear just which path you need, so you'll need to provide some more info.
Kevin Jennings
Honored Contributor
