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Altera_Forum
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14 years ago

Gate Level Simulation

Hey everyone, I have a functional model of an NLMS core running. Its simulation shows correct operation. However, I've never downloaded it onto an FPGA yet. Whi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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First, is a gate level simulation the same as downloading the circuit onto the board? If it works with the gate level simulation, will it work on the FPGA?

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Mostly, yes. However, simulations suffer from the "garbage in, garbage out" rule.

Also, simulations aren't 100% perfect. Gate level simulations don't, for example, take into account I/O signal integrity issues or power supply issues.