Gate Level Simulation

Thanks for the reply rbugalho. How would you go about fixing the timing violations?

I also don't understand what you mean by constraints. I've never used the timing simulations before. Could you please give me a little understanding as to what you mean?

Also, I specified a clock as fclk in my testbench, and used it in some of my always statements. Is that the same as specifying a clock? If not, then how do I specify it.

I know these questions are pretty basic, but this is my first time perfoming a gate level simulation, and any suggestions would be greatly appreciated.