Gate Level Simulation

EE,

constraints are used by synthesis and static timing analysis (STA), not by gate level simulation; and specifying constraints has nothing to do with the testbench.

These constraints tell the tools what timing requirements you need the design to meet.

The most basic requirement you need to specifiy is the clock frequency at which you want to run your design.

Then those tools will a) attempt to meet your requirements and b) check that your requirements have been met or not.

If you haven't constrained your design or the STA says that the requirments haven't been met*, then gate level simulation is pretty much a waste of time.

* You get a "Critical Warning: Timing requirements not met" in the final stages of compilation.

For modern Altera FPGAs, the STA tool to use is TimeQuest and Rysc has a wonderful guide on how to use it, as Dave mentioned.