Gate Level Simulation

If you're using NativeLink, setting up RTL and gate level simulation is the same thing.

You just need to use "Tools -> ... -> EDA RTL Simulation" and "Tools -> ... -> EDA gate level simulation"

From the looks of it, there's nothing wrong with the simulation. Quite simply, it's telling you that there are timing violations in the design. Hence the $hold() errors and the XXXX outputs.

Ie, it's telling you it won't work.

Thus, you need to go back and track down what's wrong.

Did you constrain your design properly (ie, specify clocks)?

Does it meet the timing constraints?

Are you using TimeQuest?

Are your testbench stimulus realistic and consistent with the constraints?