Gain control using fpga

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i have four FIR filters and i want to control the gain in the output of each filter and then sum their outputs. The result is sended to an DAC.

it is possible to control the gain in fpga?

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There's a couple of solutions;

1) Add a gain block (multiplier) between each FIR filter output and the summing block.

2) If the FIR filter coefficients are re-loadable, then use the coefficients to implement the gain function, by scaling them appropriately.

The second option requires a little care regarding the dynamic range of the signals. However, depending on the bit-widths of your signal and coefficients, the scaling may be available 'for free', eg. lets say you have a design with 16-bit data and coefficients, and the design is using hardware multiplers, because the multipliers are 18x18-bit, you have a couple of extra bits that you can use for the gain function. If that is sufficient, then you get your gain function for free.

Cheers,

Dave

Dear Dave,

thank you for your reply. i'm just wondering why everybody control the gain using an amplifier. I need to change the gain in steps of 1 db till 20 dB. If DAC can handle this?

thank you.

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thank you for your reply. i'm just wondering why everybody control the gain using an amplifier. I need to change the gain in steps of 1 db till 20 dB. If DAC can handle this?

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The reason has to do with dynamic range.

Given a B-bit DAC, you can create a signal with at-best a dynamic range of about 6dB per bit.

If you were to implement 20dB of gain variation in the digital domain, then you would be using up 3 to 4-bits of your DAC to perform that function.

If you only needed 8-bits of dynamic range, and you were using a 12-bit DAC, then great, you can do it digitally.

However, even with that level of control, if the DAC output is too small relative to whatever the voltage you need is, then you have to have an amplifier. You'd likely need this amplifier anyway, as part of an analog filter to remove higher-frequency images from the DAC output (since it has a sort-of stair-case like response for an ideal DAC).

So your two options are;

1) DAC with extra bits, digital gain control, and a fixed-gain amplifier/filter.

2) DAC with just-enough bits, and a variable-gain amplifier/filter with analog gain control (actually the control bits will be digital, but the gain on the analog signal would be 'analog').

Is that clearer?

Cheers,

Dave

Yes, but now supose im using 14 bits and i have 5 FIR filters, The filters output are 14 bits. If i sum the outputs of the filters overflow will occurs.

So how can i handle this?

I wont a 0 dbm for each FIR output seen in the DAC output.

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Yes, but now supose im using 14 bits and i have 5 FIR filters, The filters output are 14 bits. If i sum the outputs of the filters overflow will occurs.

So how can i handle this?

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First, you need to work out if you need 14-bits of precision in your FIR filter output. If you know the input signal characteristics, and the FIR filter response, then you can calculate the RMS of the signal and the RMS of the noise, and from that you can determine the minimum number of bits you require. For now, lets assume you need 14-bits, but you should check.

When you add two B-bit values together, you get worst-case bit-growth of 1-bit, so for your 5 filters, you will get a bit growth of a little over 2-bits. If your input RMS is lower than its maximum possible value, then you probably only need to grow the result by 2 bits. If the noise in your signal is random, then its variance will add, so the variance in the sum will be 5 times the variance of the input (assuming each input has the same noise), so the noise power will increase by sqrt(5) = 2.24, i.e., a little over 1-bit, so your dynamic range might increase slightly (depending on whether the 'signal' is also noise-like or whether it is coherent).

I assume you have a 14-bit DAC, and that is why you have scaled your FIR filter outputs to 14-bits. However, your sum will be around 16-bits, so you will need to convergent round the wider sum to 14-bits so that you can drive the DAC.

Does that make sense?

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I want a 0 dBm for each FIR output seen in the DAC output.

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No you probably don't. You want the largest possible signal your DAC can output, within the constraints of the sampling bandwith, and the inverse sinc filter response (assuming you have such a filter).

The DAC output power into a 50-ohm load, or the power in dBm, will be whatever the board designer decided it will be. There's not much you can do about it, other than use what your board design has. You have not provided details on that, so I can't comment more.

Cheers,

Dave

Thank you Dave.

rigth now i'm using a Cyclone III DSP kit with a DAC of 270 MSPS. I'm using this kit to test and evaulate my sistem. My project is to build an hardware with such specificacions. For now i'm just testing and writing codes in VHDL.

My quaestion is: If i have a 14 bit DAC with maximum output voltage = 1Vp.

load = 50 ohms

output power per band = 0 dbm

power adjust : 20 db in steps of 1dB.

As i said, i need to sum 5 filters output and keep the number of bits.

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Right now i'm using a Cyclone III DSP kit with a DAC of 270 MSPS. I'm using this kit to test and evaluate my system. My project is to build an hardware with such specifications. For now i'm just testing and writing codes in VHDL.

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Ok, thanks.

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My question is: If i have a 14 bit DAC with maximum output voltage = 1Vp.

load = 50 ohms

output power per band = 0 dbm

power adjust : 20 db in steps of 1dB.

As i said, i need to sum 5 filters output and keep the number of bits.

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If you used your DAC to generate a full-scale sinusoid, then the sinusoid would have a peak voltage of 1V, or RMS voltage of 1/sqrt(2)V. The power into a 50-Ohm load would be P = V^2/R = 1/(2*50) = 10mW = 10dBm. So from that analysis you can see that if you are generating a sinusoid output, you have an appropriate DAC voltage, i.e., you can generate a 0dBm signal.

However, you have not provided a specification on what the noise floor in the DAC output should be, eg., if you output 0dBm, you are not exercising the MSB of the DAC, so is 13-bits good enough? When you drop down 20dB more, you stop exercising the top 4-bits, so is 10-bits of DAC output good enough?

Its also unlikely that you are generating a sinusoid output, so you first need to determine the RMS power of a signal that is representative of what you will really be transmitting. For example, noise-like signals have large excursions from the mean, and to avoid clipping, you keep the RMS at about 1/4 of the DAC output, i.e., you've lost 2-bits.

If you have a 270MHz DAC, you can probably generate frequencies up to about 0.4 x 270MHz = ~100MHz without too much distortion. What frequencies do you need to generate?

If you are going to implement your gain control digitally, you could measuring the power of the filtered-sum (via the sum of the samples squared over some integration time), and then add a multiplier between the sum and the DAC, to increase or decrease the signal power. If your gain can be in steps of 2 (2, 4, 8, 16, etc), then you do not need a multiplier, as a right shift will do (you will also need to check whether rounding of your gain block output is required, rather than truncation).

So what requires the 20dB of gain? Is it the signal inside the FPGA, or is it the device you are driving with the DAC? If the signal within the FPGA has the 20dB of dynamic range, then you would want to adjust the power earlier in the signal processing chain, not wait until the DAC output.

Cheers,

Dave

Taking the 1 dB gain step simply as a specification, you'll need a table of gain factors and a multiplier to implement it.

According to the HSMC data conversion board schematic, the output level will be lower than +10 dBm due to the internal termination. In impedance matched setting (R120/122 populated), + 4dBm in 50 ohm should be achieved, with R121/R123 populated only + 2 dBm due to impedance mismatch.

So there will be probably a problem to achieve the specified output without an amplifier.

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Ok, thanks.

Thanks Dave.

If you used your DAC to generate a full-scale sinusoid, then the sinusoid would have a peak voltage of 1V, or RMS voltage of 1/sqrt(2)V. The power into a 50-Ohm load would be P = V^2/R = 1/(2*50) = 10mW = 10dBm. So from that analysis you can see that if you are generating a sinusoid output, you have an appropriate DAC voltage, i.e., you can generate a 0dBm signal.

i'm using the DAC to generate a white noise (14 bits LFSR - generated in fpga, maybe i should decrease the number of bits. But what happens, is the noise still be white?).

However, you have not provided a specification on what the noise floor in the DAC output should be, eg., if you output 0dBm, you are not exercising the MSB of the DAC, so is 13-bits good enough? When you drop down 20dB more, you stop exercising the top 4-bits, so is 10-bits of DAC output good enough?

I realy dont know. How do i calculate the SNR of DAC?

Its also unlikely that you are generating a sinusoid output, so you first need to determine the RMS power of a signal that is representative of what you will really be transmitting. For example, noise-like signals have large excursions from the mean, and to avoid clipping, you keep the RMS at about 1/4 of the DAC output, i.e., you've lost 2-bits.

If you have a 270MHz DAC, you can probably generate frequencies up to about 0.4 x 270MHz = ~100MHz without too much distortion. What frequencies do you need to generate?

If you are going to implement your gain control digitally, you could measuring the power of the filtered-sum (via the sum of the samples squared over some integration time), and then add a multiplier between the sum and the DAC, to increase or decrease the signal power. If your gain can be in steps of 2 (2, 4, 8, 16, etc), then you do not need a multiplier, as a right shift will do (you will also need to check whether rounding of your gain block output is required, rather than truncation).

My gain should go from -19 dB to 0 dB in steps of 1 dB. I need a multiplier or a divider (what is better, start with a -19 dbm and multiply to increse the gain or start with 0 dbm and divide to achive -19 dbm?) . Does the quantization noise apply?

So what requires the 20dB of gain? Is it the signal inside the FPGA, or is it the device you are driving with the DAC? If the signal within the FPGA has the 20dB of dynamic range, then you would want to adjust the power earlier in the signal processing chain, not wait until the DAC output.

Each one of the filters output must be 0 dbm (maximum) at the DAC output.

OBS: Do you know how to calculate spurious emission?

Cheers,

PAtrício.

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i'm using the DAC to generate a white noise (14 bits LFSR - generated in fpga, maybe i should decrease the number of bits. But what happens, is the noise still be white?).

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Are you using the LFSR to create uniform noise or Gaussian noise? The difference relates to the power in the power spectrum.

For a detailed analysis of LFSRs and examples of power spectra, see;

http://www.ovro.caltech.edu/~dwh/correlator/pdf/lfsr_tutorial.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/lfsr_tutorial.pdf)

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I realy dont know. How do i calculate the SNR of DAC?

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The quantization noise floor will be at approximately 6*B. However, all DACs have a sinc-like output response (see examples in the above doc), so you have to inverse-filter your output signal, hence you lose SNR relative to the ideal.

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My gain should go from -19 dB to 0 dB in steps of 1 dB. I need a multiplier or a divider (what is better, start with a -19 dbm and multiply to increse the gain or start with 0 dbm and divide to achive -19 dbm?) . Does the quantization noise apply?

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The quantization noise floor does not move. If you are planning on having just a noise output, then you can probably just treat the quantization noise as part of your signal. However, if you are trying to generate band-pass filtered noise, then the quantization noise sets your noise floor.

Read these;

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/esc-100paper_hawkins.pdf)

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Each one of the filters output must be 0 dbm (maximum) at the DAC output.

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That comment does not really makes any sense. There is only one output and hence the output 0dBm. If N signals are each contributing a fixed power level, then each signal has to have 1/N power, or an RMS that is 1/sqrt(N) smaller.

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Do you know how to calculate spurious emission?

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Of what? Do you have an antenna or board design you are trying to measure? You put it in an EMI chamber and measure it.

Cheers,

Dave