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Right now i'm using a Cyclone III DSP kit with a DAC of 270 MSPS. I'm using this kit to test and evaluate my system. My project is to build an hardware with such specifications. For now i'm just testing and writing codes in VHDL.
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Ok, thanks.
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My question is: If i have a 14 bit DAC with maximum output voltage = 1Vp.
load = 50 ohms
output power per band = 0 dbm
power adjust : 20 db in steps of 1dB.
As i said, i need to sum 5 filters output and keep the number of bits.
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If you used your DAC to generate a full-scale sinusoid, then the sinusoid would have a peak voltage of 1V, or RMS voltage of 1/sqrt(2)V. The power into a 50-Ohm load would be P = V^2/R = 1/(2*50) = 10mW = 10dBm. So from that analysis you can see that if you are generating a sinusoid output, you have an appropriate DAC voltage, i.e., you can generate a 0dBm signal.
However, you have not provided a specification on what the noise floor in the DAC output should be, eg., if you output 0dBm, you are not exercising the MSB of the DAC, so is 13-bits good enough? When you drop down 20dB more, you stop exercising the top 4-bits, so is 10-bits of DAC output good enough?
Its also unlikely that you are generating a sinusoid output, so you first need to determine the RMS power of a signal that is representative of what you will really be transmitting. For example, noise-like signals have large excursions from the mean, and to avoid clipping, you keep the RMS at about 1/4 of the DAC output, i.e., you've lost 2-bits.
If you have a 270MHz DAC, you can probably generate frequencies up to about 0.4 x 270MHz = ~100MHz without too much distortion. What frequencies do you need to generate?
If you are going to implement your gain control digitally, you could measuring the power of the filtered-sum (via the sum of the samples squared over some integration time), and then add a multiplier between the sum and the DAC, to increase or decrease the signal power. If your gain can be in steps of 2 (2, 4, 8, 16, etc), then you do not need a multiplier, as a right shift will do (you will also need to check whether rounding of your gain block output is required, rather than truncation).
So what requires the 20dB of gain? Is it the signal inside the FPGA, or is it the device you are driving with the DAC? If the signal within the FPGA has the 20dB of dynamic range, then you would want to adjust the power earlier in the signal processing chain, not wait until the DAC output.
Cheers,
Dave
Honored Contributor
