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Altera_Forum
Honored Contributor
Honored Contributorfull comilition but no logic elments?????
hi everyone,
i designed a nonpiplined mips, it includes two difrent ram memorys, one for the program and one for the data. each modul compiles sepratly and as i tried to put the all system under one entity it get compiled but on the compiltion report it says that no logic elments were used. i cheaked all the modules again , they are all conected properly. anyone got an idea whats going on there? thanks i have attached a screenshot of thee comilition report i would also note that i get it only on when i try to compile that top level entity,as i cheaked all lower entities, they were all compiled with their logic usage included thaks again6 Replies
Altera_Forumwhy dont just put the in one chip
- Altera_Forum
or you connected the clock enable to '0'
- Altera_Forum
This happens, if the design either has no outputs or the outputs don't depend on any input pin, because of missing logic connection. Although you claimed to have checked the module connections, you obviously missed something important, e.g. the clock input.
- Altera_Forum
i do get a warninig stating that that nodes are synthsized away?
what do i do to get rid of it? - Altera_Forum
Assuming your design has outputs, look at the messages in the analysis and synthesis stage and make sure you don't see anything stating that your outputs are stuck high/low or logic being synthesized away.
- Altera_Forum
Have you any outputs from your design?
