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Altera_Forum's avatar
Altera_Forum
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15 years ago

full comilition but no logic elments?????

hi everyone, i designed a nonpiplined mips, it includes two difrent ram memorys, one for the program and one for the data. each modul compiles sepratly and as i tried to put the all system unde...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Assuming your design has outputs, look at the messages in the analysis and synthesis stage and make sure you don't see anything stating that your outputs are stuck high/low or logic being synthesized away.