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Altera_Forum's avatar
Altera_Forum
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15 years ago

fsm debuging

fsm debugging

Hi I started to check the fsm on real time and got some strange behaviors.

I tried working with SignalTap but I didn't like the way he display the waves and we didn't really get how to work with him.

So I went to ModelSim and created a test bench and got the next wave form

There is a lot of signals there but I can see that the logic is working, the only problem is that the pwm is not working (the signal in red) and I don't know why.

This design works when all the code is in the same file (without components)

I had the same thing with the encoder enable nut I succeeded in solving it by giving him a default value of '0'.

for another way to look were the program got stuck I used a 7 seg display

where at the commands bk,fd - 1,2 the fsm got stuck at state 15

and in the commands rt,lt - 3,4 the fsm got stuck at state 10

33 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I have puted the simulation result at a doc because the gif isn't clear

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    With components and 'red' values showing in modelsim when I assume you're trying to drive the pwm outputs, this might be multiple drivers. With a glance for this over your file, that's not evident, but might be hidden in your components for your pwm drivers (steer, motion).

    It's best to simulate first. Don't rely on tools like signal tap except for integration. When you develop a module, simulate it. Better yet, have someone else do it (independent verification).

    Jerry
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    thanks for your replay

    --- Quote Start ---

    Better yet, have someone else do it (independent verification).

    Jerry

    --- Quote End ---

    well I have no one to check my design because I started to learn VHDL a few months ago by writing codes to a project I am doing and the people here help me a lot with every question I didn't succeeded on solving by myself , with a book or with Google.

    should I look in the component for the problem or in the fsm ... has i said before and your answer strengthen my believe that the problem is at the component and not in the fsm because when I put everything in one file it's working ( most of it any way I will solve the rest later on)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The enable signals problem was solved earlier by giving them a reset value in the fsm design ( I guess I forgot)

    For the pwm signals I have posted another picture of the problem according to the modelsim

    Do I need to put a flip-flop between internal signal that connects to the real world like in the case of the pwm component (pwm signal ) and the fsm design (M_P_signal,S_P_PWM)

    In order to synchronized between them?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I have putted an sync reg consisted from 3 FF and it's solved the problem

    I thought that a component is a part of the system there for If the system is synchronized I don't need a sync reg between like I need in the case of getting data from the real world like a sensor... am I right?

    I am sorry in asvance for posting my every thought
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The synthesisor wont balance your paths for you. You still need to ensure the pipeline lengths match along all paths.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    What do you mean exactly when you said 

    ensure the pipeline lengths match along all paths

    do I do that with a sync reg like I did or in another way?

    how do I know that the pipe length is match ?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    sync registers will lengthen pipleines. And you should know how long the pipelines are because you made them.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    is sync reg are the best solution for pipeline length match because they causing the all process to take a longer amount of time.

    And should I count in every component how much clocks he needs in order to finish the process and then take that into account in the fsm design