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Altera_Forum
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Honored Contributorfsm debuging
fsm debugging
Hi I started to check the fsm on real time and got some strange behaviors. I tried working with SignalTap but I didn't like the way he display the waves and we didn't really get how to work with him. So I went to ModelSim and created a test bench and got the next wave form There is a lot of signals there but I can see that the logic is working, the only problem is that the pwm is not working (the signal in red) and I don't know why. This design works when all the code is in the same file (without components) I had the same thing with the encoder enable nut I succeeded in solving it by giving him a default value of '0'. for another way to look were the program got stuck I used a 7 seg display where at the commands bk,fd - 1,2 the fsm got stuck at state 15 and in the commands rt,lt - 3,4 the fsm got stuck at state 1033 Replies
Altera_ForumI need to think about that because I don't have a synthesize problem I am working on quartus all the time and only in the end before I am checking my code for real I am going to modelsim for simulation.
The piace of pwm code I wrote does works when it stand by himself and there was no problem in using the time package then. More over I am still using it in the main entity because temporlly I have solved the problem by adding another port called duty_cycle tothe pwm component and he his calculated by the same generics... so I still don't see why it's a problem I can only agree that "logic has no concept of time"- Altera_Forum
Hi,
Logic has no concept of time. VHDL can be of type time, but you can't expect anything to happen in logic after some number of ms, ns, etc... So change all your actions (duty_cycle, min_cycle, neutral_cycle) to be integer counters based on a ms timer count ( this timer count is based on a system clock, which I assume is 50 MHz. Count out ms using timers, then make decisions based on timer values.... you can't compile time into silicon. I think Tricky brings up a critical point of FPGA / ASIC design. In case this was too subtle: "Before you simulate, make sure your can synthesize the code." If you simulate something that can't become logic, it's obviously a waste of time. Jerry - Altera_Forum
helo again,
I think I found the reason why the robot didn't responed to the commands Can I inside a component create a constant and caculate its value from generics constans like this: generic ( DC: time:= 17 ms; clock_period: time:= 20 ns; max_pulse: time:= 1 ms; min_pulse: time:= 2 ms; ); constant duty_cycle: integer:= DC/clock_period; --850000 constant min_cycle: integer:= min_pulse/clock_period; --50000 constant max_cycle: integer:= max_pulse/clock_period; -- 100000 constant neutral_cycle: integer:= neutral_pulse/clock_period ; --75000 and then ask if (Counter = duty_cycle) then I think I can't and that the value of the constant duty_cycle is zero thougts? - Altera_Forum
Hello all
My mistake was much more primitive then Tricky as said. I have defined in the test bench things I shouldn't have like, mapping internal components of the top level entity. That’s way the tb didn't work but I still didn't found the reason for why does the code isn't working Please correct me if I am wrong - Altera_Forum
if I will put a signal between the two ports will it solve the problme ?
(will is solve it also in practice as well) - Altera_Forum
As for my suggestion to assign the internal pwm component port to a pin
it can't be done because then the sestem clk and reset are not driving him, and assigning another port in the pwm component is causing the same multi driver problem as before. who can I solve it ... I didn't think that connecting an output port from a component to another output port will be so frustrating. - Altera_Forum
I didn't compile the test bench in quartus only the main entity and its components.
the flag is a port I wanted to add in order to sign the main entity that the process is over but I can also take the pwm port from the component and assign it directly to a pin but then it want be visual in the main entity - Altera_Forum--- Quote Start --- ok know I see it ... in quartus the conpiler didn't gave my any warnings when I changed the signal type to std_ulogic. --- Quote End --- The error is in the testbench, which you should not be compiling in quartus. As for the flag - why not just create another port?
- Altera_Forum
ok know I see it ... in quartus the conpiler didn't gave my any warnings when I changed the signal type to std_ulogic.
so has you have said before I need to use a flag in order to inform the main entity that the process is done because I can't use the same port in a component in order to drive an outside signal port ... but can I assign that port within the component to be an outside port? thanks a lot - Altera_Forum
The problem is because m_p_pwm is connected to the fsm and the motion_pwm.
I did what I told you, and changed m_p_pwm to a std_ulogic in the testbench, and instantly got an error. You can only connect m_p_pwm to one thing.
