Honored Contributor
Honored ContributorHi,
Logic has no concept of time. VHDL can be of type time, but you can't expect anything to happen in logic after some number of ms, ns, etc... So change all your actions (duty_cycle, min_cycle, neutral_cycle) to be integer counters based on a ms timer count ( this timer count is based on a system clock, which I assume is 50 MHz. Count out ms using timers, then make decisions based on timer values.... you can't compile time into silicon. I think Tricky brings up a critical point of FPGA / ASIC design. In case this was too subtle: "Before you simulate, make sure your can synthesize the code." If you simulate something that can't become logic, it's obviously a waste of time. Jerry
