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Altera_Forum's avatar
Altera_Forum
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15 years ago

fsm debuging

fsm debugging Hi I started to check the fsm on real time and got some strange behaviors. I tried working with SignalTap but I didn't like the way he display the waves and we didn't really get ho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ok know I see it ... in quartus the conpiler didn't gave my any warnings when I changed the signal type to std_ulogic.

so has you have said before I need to use a flag in order to inform the main entity that the process is done because I can't use the same port in a component in order to drive an outside signal port ... but can I assign that port within the component to be an outside port?

thanks a lot