fsm debuging

I need to think about that because I don't have a synthesize problem I am working on quartus all the time and only in the end before I am checking my code for real I am going to modelsim for simulation.

The piace of pwm code I wrote does works when it stand by himself

and there was no problem in using the time package then.

More over I am still using it in the main entity because temporlly I have solved the problem by adding another port called duty_cycle tothe pwm component and he his calculated by the same generics...

so I still don't see why it's a problem

I can only agree that "logic has no concept of time"