Frequency of StratixIV

Hey Aflatoun,

I believe I understand your problem. You have a program that you are running on your processor. This program takes about the same amount of time whether your system clock is one frequency or a faster frequency. Is this a good explanation of your problem? I looked at your qar and did not find any software. Based on the simplicity of the software, most of the time taken could be initialization of the FPGA and your system rather than time spent running your program. So it is possible that if make your program more complicated, with more loops, that it will take a longer amount of time. Be careful with this approach though, since the software compiler can optimize out what it sees as useless commands. Please let me know if this doesn't help.

Thanks,

Ben

Hi Protocol,

Are you understand the problem or no?

Of course friend, you will find it in attached file.

Thanks

I make as you said. But always i find the same time.

I explain to you what i do exactly. I have the SOPC given by the stratix IV GX. It work with simple program hello_world, i try to change the software, in the end i puts the execution time of my program. When i make a debug as NIOS II, i obtained 300ms.

Every time i change the frequency, i notes that the time always 300ms.

I change first the frequency under SOPC (input of PLL is 50 MHZ, pll.co=150Mhz, ppl.c1=150 MHZ) and i finished by generate. As you said,i uncomment derive_pll_clocks -create_base_clocks and add the three file "CPU.sdc, pll.sdc, and tse_mac_constraints.sdc" to timing analyser, Finally i compile my project. when i debug my program after building i obtained also 300 ms.

yes that's i do, uncomment the line derive_pll_clocks -create_base_clocks" and add pll.sdc. Sorry what's the timing file.

I hope that will work.

think you protocol.

Hello Protocol Enginner,

Yes i have other sdc file "CPU.sdc, pll.sdc, and tse_mac_constraints.sdc". There are two line contain derive_pll_clocks. wich line i uncommentig. When i try to go in timeQuest under assignement setting i find two file CPU.sdc and tse_mac_constraints.sdc , and the pll.sdc not included.

Thanks friend,

Hello Aflouton,

Do you have any other sdc files that you are using in your project? If not, without including timing constraints in your project, you won't get correct timing analysis. You might try uncommenting the derive_pll_clocks line mentioned before in the pll.sdc file, which will derive the timing constraints from the pll in your SOPC project. You will also need to make sure the sdc file is included in your project(in Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file).

-Ben