Frequency Divider Timing Req. Never Met

I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst case setup slack of -5.547:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--
entity freq_div is
    port(     clkin : in std_logic;
            reset : in std_logic;
            clkout: out std_logic);
end entity;
--
architecture main of freq_div is
--
--
signal cnt0 : unsigned(4 downto 0);
--
begin
    --
    process(clkin,reset)
    --
    begin
        if reset='0' then
            cnt0 <= "00000";
        elsif clkin'event and clkin='1' then
            if cnt0 = "10000" then
                cnt0 <= "00000";
            else 
                cnt0 <= cnt0 + 1;
            end if;        
        end if;
    end process;
    --
    --
    --
    clkout <= cnt0(4);
    --
end architecture;