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Altera_Forum
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14 years ago

Frequency Divider Timing Req. Never Met

I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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To analyze timing of domain crossing data, TimeQuest must be able to determine their exact relation of both clocks. This is easy in the usual case of both clocks derived from the same input clock. Otherwise both are treated as unrelated.

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Oops? IMHO if not explicitly told by using 
set_clock_groups  -asynchronous -group { clk1 clk2_derived_from_clk1 } -group {clk3_unrelated}  ...
TQ treats all clocks as being related and may thus flag timing errors between certain clocks, even if you have added anti-metastabiity provisions.