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Altera_Forum
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14 years ago

Frequency Divider Timing Req. Never Met

I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Oops? IMHO if not explicitly told by using 
set_clock_groups  -asynchronous -group { clk1 clk2_derived_from_clk1 } -group {clk3_unrelated}  ...
TQ treats all clocks as being related and may thus flag timing errors between certain clocks, even if you have added anti-metastabiity provisions.

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Those kind of clocks should be considered as asynchronous group like this then. Thank you very much.