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Altera_Forum
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14 years ago

Frequency Divider Timing Req. Never Met

I am trying to make a freq. divider and tried many VHDL solutions on the web. Most of them worked but TimeQuest always tells timing requirements did not met. Here is one code that worked with a worst...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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To analyze timing of domain crossing data, TimeQuest must be able to determine their exact relation of both clocks. This is easy in the usual case of both clocks derived from the same input clock. Otherwise both are treated as unrelated.

The other point is that "design works in practice" doesn't guarantee that there are no timing violations and possibly infrequent random errors.

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So far I haven't met any error but if I have in the future I will change the whole design. Than you very much for your replies.