Forum Discussion
Honored ContributorFrame buffer IP
We use 2 frame buffer IPs in our design.
1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We do not use the read & dout of this Frame buffer . So, these unused interfaces are connected to an empty dummy component (reference to the service request no. 10773449 ) 2- The second frame buffer: should read the data written by the first Frame buffer in the used SDRAM and gives this data to the DVI out IP (VGA_out_INST). W e do not use the write & din of this Frame buffer. So; these unused interfaces are connected to the same dummy component. Taking into consideration that, the dummy component interfaces are Avalon. Kindly advise about the following 1- Is it applicable to use a Frame buffer to write data in SDRAM and another Frame buffer to read this data from the same SDRAM as described above? 2- How to make sure that the second frame buffer reads the data from the same addresses used by the first frame buffer for writing in the SDRAM? This question is because the addresses are nit indicated when we instantiated the frame buffer in SOPC builder28 Replies
Altera_ForumI think you'll have to make a custom component for that, with one sink and two sources. Just connect all the signals from the sink to both sources, and for the 'ready' signal, do an 'and' between the signals from the two sources and put the result on the sink. I think it should work.
Depending on what you connect your component to, you may need to put some FIFOs to handle the cases when your two IPs aren't ready at the same time.- Altera_Forum
In our design using SOPC Builder we want to connect the output port (Avalon stream source) of an IP (clocked video output) to 2 other IPs. But it is not accepted. The clocked video output accepts to be connected to one IP only.
Kindly advise if there is any block or component or certain IP can be used to solve this problem. - Altera_Forum
Thank you for your reply
- Altera_Forum
I don't have much experience using SGDMA or Ethernet, so I am not going to comment on your overall block diagram. However, there are a couple things that come to mind:
1. Based on the block diagram, it appears that you are trying to send uncompressed 1080p video over ethernet. If you are trying to actually send a full 24 bits/pixel 60 fps, this would be over 3 Gbits/s of data. You won't be able to send that fast using the Altera TSE. 2. Assuming the rest of your block diagram is okay, I still think you should not be using the frame buffer IP at all. For your second frame buffer, you should be able to use the Altera Frame Reader instead. The frame reader lets you specify the SDRAM address to read from. For your first frame buffer you could write a custom component that just writes the video data to whatever address you want. - Altera_Forum
Kindly see the attached word file
- Altera_Forum
The attached file is the testing block diagram
- Altera_Forum
Thank you for your reply.
Usually, one Frame Buffer is used for reading & writing operations. However, I want to separate the reading apart from the writing using 2 different Frame Buffers because there is some processing required after the writing and before the reading (Ethernet TX&RX). This is shown in the attached brief block diagram. 1- Please confirm that: this block diagram is suitable for testing purposes. 2- If it is suitable, how can we choose the SDRAM address for reading and writing operations done by the Frame Buffer and SGDMA? - Altera_Forum
Is there a reason you are not just using one frame buffer as it is intended to be used?
Or are you trying to manipulate the data in SDRAM as it passes through the system? In this case, it may be easier to just write your own custom IP instead of trying to warp the frame buffer into doing something it was not designed for. The Altera Frame Reader may be usable as is in you application for the output side.
