Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Frame buffer IP

We use 2 frame buffer IPs in our design. 1- The first frame buffer: takes its data (din) from DVI Input IP (VGA_IN_INST) and writes this data into an SDRAM through the SDRAM controller. We d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I think you'll have to make a custom component for that, with one sink and two sources. Just connect all the signals from the sink to both sources, and for the 'ready' signal, do an 'and' between the signals from the two sources and put the result on the sink. I think it should work.

Depending on what you connect your component to, you may need to put some FIFOs to handle the cases when your two IPs aren't ready at the same time.