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Honored ContributorFractional N PLL implimentation in IP possible on Cyclone V and max10?
Hi guys.
So I have a dedicated PLL chip that can phase lock an output clock of tens of Megahertz to an input clock of tens of Hertz, or million fold, using fractional N PLL. Simple dividers will cause too much jitter at these multiplications, and divide by N PLL are necessary. It's a great chip but I'm wondering if the same can be accomplished in an FPGA such as the Cyclone V or Max10 with the new Mega_Wizard. Let's say I want to phase lock a PPL output clock at 50MHz. to an input clock of 50Hz. - it looks like this kind of performance may be possible based on the information here: https://www.altera.com/products/fpga/features/stxv-fpll.html , but i'm not sure. Thank for your help. Cheers, Bob16 Replies
Altera_ForumThanks, gj_leeson.
- Altera_Forum
It will take more than logic to build your 50Hz to 50Mhz PLL. Not achievable within an FPGA IMHO.
- Altera_Forum
Thanks, Anard.
- Altera_Forum
Hi,
Yes you can have your own logic for your design. Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation) - Altera_Forum
Hi Anard. Thanks for your reply.
So I guess that means I would have to build the rest of this 50Hz. to 50MHz. PLL myself, on the FPGA, from logic. I'm assuming this is possible as I have a chip that can do it. Should this be possible with ALtera FPGA and tools. Thanks for your help. Cheers, Bob - Altera_Forum
Hi,
Cyclone V supports PLL input clock range of 5MHz to 670MHz. https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf Max10 V supports PLL input clock range of 5MHz to 470MHz. https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf Let me know if this has helped resolve the issue you are facing or if you need any further assistance. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
