1 - The clock pins on the FPGA only have significance if you actually use them. The fact that they are labeled as dedicated clock pins does NOT mean that you must connect a clock to them or the FPGA will cease to work. The FPGA will do whatever you tell it to do.
2 -If you truly do not have a clock, you are of course forced into an asynchronous design. This is fine but asynchronous logic design has it's own caveats that must not be ignored particularly when constraining timing.
3 - You can provide a clock to the FPGA on a pin other than the dedicated clock pins. The dedicated pins are ideal because the internal circuitry has been designed to provide the cleanest possible clock via the dedicated pins. You obviously have some pins connected between the CPLD and the FPGA. You could therefore dedicate one of these pins to be a clock (assuming your CPLD has a clock). Then the CPLD could provide the clock to the FPGA.
4 - If you really are only going to use the FPGA for combinatorial or asynchronous logic, then you have no need for a clock in the first place. If however you are trying to figure out how you can accomplish what you need without a clock simply because you forgot to give it one in the first place, then go back and provide a clock.
Jake
Honored Contributor
