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Altera_Forum
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17 years ago

FPGA without clock?

Hello everyone:), I want to use FPGA simply as a glue logic as I can't think of enough I/O pins available in my CPLD. I don't want to give any clock to the FPGA as the clock is ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Clock signals are not mandatory, so you may decide to use the FPGA as you used the CPLD before. But be sure that an asynchronous design is enough reliable for your system. Every time a synchronous solution is more reliable and more stable compared to an asynchronous one. So, if you have a chance to introduce a clock, I would suggest you to use it. Otherwise, go on with your asynchonous design and check the result.