Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

FPGA Selection for more Speed

I am using Cyclone iii for Software Defined Radio. Timing analysis shows a limit at about 120 MHz for the code. I want to double the sampling clock speed to 200 MHz. How can I select the appropriate FPGA without running endless timing analysis. I tried it with Stratix ii and came close to the new limit but still want to have a margin.

Any recommendations are welcome.

Gerd

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You need to see if its your code that is the limit.

    Try doing timing analysis for a simple register-to-register path within the FPGA (not an IOE-to-register path though, as that will be slower).

    I would expect that you can get fmax much higher than 120MHz in a Cyclone III (assuming a high speed grade device).

    I use ancient FLEX10K devices at 125MHz with no issues.

    You most likely need to pipeline your code to reduce the register-to-register paths.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Dave,

    thanks for your reply.

    The code is in Verlog and I am not experienced enough to judge if there is a chance to pipeline the code. Are there any tools to pipeline the code?

    Would you be willing to have a look at the code for an estimation what could be achievable?

    Gerd
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi Gerd,

    Reading code is generally pretty difficult without some sort of higher-level documentation.

    You mention that this is for an SDR system. If you have a block diagram of the SDR processing stages, then it should be pretty obvious where pipelining can occur.

    For example, lets say you have an ADC interface to a filter, and then a processing block, and say more filters, and then the signal goes back out to a DAC.

    Each one of those 'components' can be analyzed in isolation to determine its register-to-register performance. The component with the worst performance is the one that needs to be fixed.

    If that component is a black-box, eg., an Altera FIR filter IP component, then you would see if you can regenerate the component using a different combination of settings.

    Trying to optimize a design only from a high-level is pretty difficult. The timing and analysis tool will point you to the slowest component in the overall design. However, that information is much more useful if you start with design components where you know the maximum operating frequencies of the individual components (in the target FPGA).

    To start with, you can create a synthesizeable design where individual components can be inserted. Eg., lets say all your DSP components are Avalon-ST components with sink and source ports. Create data source and sink RAM components, and connect each component into the system. Place-and-route the design and see what the fmax is. Repeat for all components. If they all have fmax > 200MHz, then you will have confidence that the components are all pipelined appropriately.

    Cheers,

    Dave