FPGA Selection for more Speed

Hi Gerd,

Reading code is generally pretty difficult without some sort of higher-level documentation.

You mention that this is for an SDR system. If you have a block diagram of the SDR processing stages, then it should be pretty obvious where pipelining can occur.

For example, lets say you have an ADC interface to a filter, and then a processing block, and say more filters, and then the signal goes back out to a DAC.

Each one of those 'components' can be analyzed in isolation to determine its register-to-register performance. The component with the worst performance is the one that needs to be fixed.

If that component is a black-box, eg., an Altera FIR filter IP component, then you would see if you can regenerate the component using a different combination of settings.

Trying to optimize a design only from a high-level is pretty difficult. The timing and analysis tool will point you to the slowest component in the overall design. However, that information is much more useful if you start with design components where you know the maximum operating frequencies of the individual components (in the target FPGA).

To start with, you can create a synthesizeable design where individual components can be inserted. Eg., lets say all your DSP components are Avalon-ST components with sink and source ports. Create data source and sink RAM components, and connect each component into the system. Place-and-route the design and see what the fmax is. Repeat for all components. If they all have fmax > 200MHz, then you will have confidence that the components are all pipelined appropriately.

Cheers,

Dave