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Altera_Forum
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15 years ago

FPGA Selection for more Speed

I am using Cyclone iii for Software Defined Radio. Timing analysis shows a limit at about 120 MHz for the code. I want to double the sampling clock speed to 200 MHz. How can I select the appropriate ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Dave,

thanks for your reply.

The code is in Verlog and I am not experienced enough to judge if there is a chance to pipeline the code. Are there any tools to pipeline the code?

Would you be willing to have a look at the code for an estimation what could be achievable?

Gerd