Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

FPGA Selection for more Speed

I am using Cyclone iii for Software Defined Radio. Timing analysis shows a limit at about 120 MHz for the code. I want to double the sampling clock speed to 200 MHz. How can I select the appropriate ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You need to see if its your code that is the limit.

Try doing timing analysis for a simple register-to-register path within the FPGA (not an IOE-to-register path though, as that will be slower).

I would expect that you can get fmax much higher than 120MHz in a Cyclone III (assuming a high speed grade device).

I use ancient FLEX10K devices at 125MHz with no issues.

You most likely need to pipeline your code to reduce the register-to-register paths.

Cheers,

Dave