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MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

FPGA resource issue of Cyclone 10 GX devices

Hello Guys, We used 10CX220F780 before. Now one of our new application will switch to use 10CX105F780. Because both of them are package compatible, we only need to check some special logic physical ...
Core Logic
MinzhiWang's avatar
MinzhiWang
Icon for Occasional Contributor rankOccasional Contributor
2 months ago

Hi Fakhrul,

The above messages I can get from datasheet. However, the doubt I have is why they have same LAB numbers? According to the same X/Y locations, I think they have same LAB numbers. Please help to explain about this.

 

In our application cases, we wanted to constrain some nodes to specified physical LAB locations. So when we switch from 10CX220F780 to 10CX105F780 we are afraid to use those unavailable LAB resources.

 

As you said, 10CX220 has about 80330 ALM and 10CX105 only has 38000 ALM. So they should have twice difference. We also have 50% chance to touch those unusable LABs?

Thanks

FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hi Minzhi,
 

What you are seeing is expected.

Although 10CX220F780 and 10CX105F780 are package-compatible and may show a very similar Chip Planner X/Y map, this does not mean they have the same usable LAB resources. The Chip Planner view is mainly the physical coordinate/floorplan representation, while the actual legal resources are determined by the selected device.

Therefore, some fixed LAB locations used on 10CX220F780 may not be available on 10CX105F780, even if the same coordinates are shown.

Recommended next step:
1. Change the target device to 10CX105F780
2. Run a full compilation
3. Review the Fitter messages and post-fit Chip Planner for the constrained nodes


If the assignments are legal, Quartus will accept them. If not, the Fitter will report the unavailable/illegal locations and those constraints should be updated.

This should clarify why the same X/Y display does not imply the same LAB count.


Regards,
Fakhrul

  • MinzhiWang's avatar
    MinzhiWang
    Icon for Occasional Contributor rankOccasional Contributor
    2 months ago

    Hi Fakhrul,

    I think that it's very ugly for user to use. We don't know which LABs are usable or unusable even after full compilation. So we often encounter error like " cannot place 4/6 nodes into a single ALM". The ALM would be illegal because ALM pins can not be routed.

     

    Or, even placement are accepted, the routing will be hold for more than 2 hours. You know, our application can finish compilation within 20 minutes. 

     

    We are blinded before we begin to compile our project. What just I want to know is which LABs are usable/illegal for 10CX105F780 from ChipPlanner?