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SnehalB's avatar
SnehalB
Icon for New Contributor rankNew Contributor
3 years ago

FPGA Reconfig fails from other address location in S25FL256L QSPI, but works at 0x000 for ota updat

Hi ,

We are trying to flash QSPI from FPGA with used logic code using Generic serial flash controller IP as OTA update.

We are trying to flash two image IMAGE1 at 0x0000_0000 location & IMAGE2 at 0x0100_0000 location of flash.

Then booting into one of these using remote reconfig updated block ip from intel.

Previously we have successfully validated our code on intel cyclone gx board with EPCQ256 flash. Now we are trying to test it on our cyclone V e board with cypress S25FL256L flash

We are able to write IMAGEs at 0x0000_0000 location successfully and also able to boot the fpga with it,

But when we tried to flash images at other locations (0x0080_0000 / 0x0100_0000) we are able to write successfully ,but not Able to boot fpga from that image using remote reconfig updated ip, and fpga reconfiguration fails and reverts back at 0X0000_0000 location image.

We tried to read remote reconfig status error register , and value is 0x00, means no error (watchdog timeout/CRC/nconfig none of this)

We tried using configuration device setting as EPCQ as well S25FL256 in remote update ip with both the above address, but no success.

Can you please check intel with this support!

thanks & regards,

Snehal Buche

10 Replies

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi SnehalB,

    Good day. In order to have a better understanding and narrow down to possible causes. If you can answer the following questions I'll appreciate it.

    1. Assuming the forum case (FPGA Reconfig fails from other address location in S25FL256L QSPI, but works at 0x000 for ota updat) is raised by the same customer, referring to the "OTA update", could you explained the details and how it is being performed? The reason I'm asking is per my understanding there's no documentation explaining on the integration of OTA programing with Generic serial flash controller IP.
    2. By referring to "remote reconfig updated ip", do you mean Remote Update Intel® FPGA IP or Remote System Upgrades feature that is dedicated in the Cyclone V circuitry?
    3. Could you elaborate on how the application is being performed eg. Which configuration scheme, or which interface the ECPQ is being programmed etc?

    Looking forward to your reply.

    Regards,

    Fakhrul

    • SnehalB's avatar
      SnehalB
      Icon for New Contributor rankNew Contributor
      3 years ago

      Hi fakhrul,

      1. Assuming the forum case (FPGA Reconfig fails from other address location in S25FL256L QSPI, but works at 0x000 for ota updat) is raised by the same customer, referring to the "OTA update", could you explained the details and how it is being performed? The reason I'm asking is per my understanding there's no documentation explaining on the integration of OTA programing with Generic serial flash controller IP.

      --> Refer last question

      1. By referring to "remote reconfig updated ip", do you mean Remote Update Intel® FPGA IP or Remote System Upgrades feature that is dedicated in the Cyclone V circuitry?

      --> Yes

      1. Could you elaborate on how the application is being performed eg. Which configuration scheme, or which interface the ECPQ is being programmed etc?

      --> QSPI clock frequency we used 25/15Mhz(both is tested)

      --> we are currently using only 4byte addressing in Asx1 mode with all sector unprotected for flashing

      --> hi please refer below block diagram , every logic is controlled by USB packet (cmd and data). Also as we said below logic flow is validated in cyclone gtx board with EPCQ256 flash for both the address and image successfully. same logic is ported on cyclone v e board we have.

      top level diagram

      this is performed from image at address location 0x0000 or in SRAM (same image just difference in User LED for image differentiation & identification) . from this image we performed flashing at image 2 location (image 2 is different from image1 with not ota support and only has watchdog timer reset). Already validated and working great in gtx board.

      flow for our image handling. Note for all situation of reconfig back to 0x0000 location, we have reconfig status register read which mentioned error/reason of reconfig back which is validated and working great in gtx board. but in our situation register always reads 0x00 for all failed case in image 2 location, request you to please again read our problem statement raised to get clear idea.

      in REconfig block we are setting, ota_configuration read--> ANF bit setting-->watchdog_en-->watchdog timer set-->reconfig page set-->reconfig (done after image is flashed, controlled via usb cms packet also)

      we also tried removing watchdog circuitry but no result., same issue.

      for Flash programming we followed step --> initial setup --> unprotect flash --> erase sectors --> program flash --> protect --> done

      note : here same logic is used for all image , just a base address parameter is updated for target location. (alreadty validated and working great in gtx board.)

      thanks & regards,

      snehal buche

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi SnehalB,

    Another point to clarify is, can you confirm the part number of the cypress S25FL256L flash that is being used on our cyclone V e board? The reason I'm asking is as per Cyclone® V E FPGA Development Board Reference Manual (PDF), the flash device is from Numonyx, PC28F512P30BF.

    In connection wise also, based on the board block diagram on the Cyclone V GT, the EPCQ is directly connected to the Cyclone V GT board, in contrast, on the Cyclone V E the EPCQ and flash device has to go through the MAX V.

    Regards,

    Fakhrul

  • SnehalB's avatar
    SnehalB
    Icon for New Contributor rankNew Contributor
    3 years ago

    HI ,

    • development gtx board we used was from teraasic

    Terasic - DE Boards - Cyclone - Cyclone V GX Starter Kit

    • And Cyclone v E board we are using is our custom development board using (5CEBA8C8 part number).
    • Flash we are using is S25FL256LAGNFB010 from infineon. we have directly connected flash to fpga AS configuration pins. in your above diagram intel max v and qspi connection is used when we want to have QSPI flashing via Active serial programming from quartus programmer. But when we want QSPI JTAG programming from programmer, we required SFL image on fpga and direct flash connection. Both of this case we have already encountered & tested in the GTX development board.

    But for our custom cyclone v e board only QSPI JTAG programming is possible as we dont have intel max v onboard. But besides this,on-field both of the option is not available for ota update of fpga image. for that we required below designed setup only

    So please consider, above mentioned original scenario & issue ,and help us to resolve problem.

    thanks ,

    Snehal Buche

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hello,


    We need more details information to debug this case. Can you send us the board schematic related to the FPGA configuration so we can review them?


    please send the sch to email : mohd.fakhrul.rozi.ahmad@intel.com


    regards,

    Farabi


  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi SnehalB,


    I wish to follow up with you about this case. Do you have any updates for the questions above?

    Otherwise, this thread will be idling and marked as inactive, thus it will be transitioned to community support because there is no update received from you in a while.


    Regards,

    Fakhrul



  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    As we do not receive any response from you to the previous notification that we provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.