FPGA programming: Block Design files or Verilog line by line programming?

Question

Just starting to learn Quartus for FPGA programming. I'm coming from a CPLD programming background.

I'm impressed with the Block Design files programming approach. This YouTube demo is excellent:

While my applications will be simple probably not much more than a few CPLDs I worried if there will be limitations in what I can do later on.

Also looking at the final Verilog type source type code it seems very complex and I worried that I will fill up the FPGA inefficiently.

What are the pros and cons of both approaches.

John

altera_forum · Answer

Using BDF or Verilog can produce the same results. They will both map to the same hardware.

But while some like BDF for the graphical style, it has some severe drawbacks:

1. Doesnt work well with version control. Moving a block without changing any connections will look like a massive difference

2. Doesnt Port to another vendor

3. Cannot be simulated natively

4. Difficult to document - cannot add comments easily or meaningfully.

5. Large BDF files with too much detail can be very hard to understand.

HDL can do all of the above, and in companies or larger projects they are very important.

So while BDF may help you understand an architecture, you soon get used to reading HDL and how it is structured.

altera_forum · Answer

Verilog is pretty easy to learn.  Start here:  https://www.altera.com/support/training/course/ohdl1120.html

altera_forum · Answer

Thanks Tricky, very useful/informative John

altera_forum · Answer

I can see numerous courses listed but cannot seem to get an actual video played. The intel/Altera site seem to keep on going back to register etc.

What is the "trick" URL to play an actual video tha is a good introduction to Verilog programming.

altera_forum · Answer

You have to register for the training with a free myAltera account.

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