FPGA programming: Block Design files or Verilog line by line programming?

Using BDF or Verilog can produce the same results. They will both map to the same hardware.

But while some like BDF for the graphical style, it has some severe drawbacks:

1. Doesnt work well with version control. Moving a block without changing any connections will look like a massive difference

2. Doesnt Port to another vendor

3. Cannot be simulated natively

4. Difficult to document - cannot add comments easily or meaningfully.

5. Large BDF files with too much detail can be very hard to understand.

HDL can do all of the above, and in companies or larger projects they are very important.

So while BDF may help you understand an architecture, you soon get used to reading HDL and how it is structured.