FPGA INTERFACING with ADSP BF548?

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I am in need to interface four FPGAs to ADSP BF548 processor. what type of interface can i use??

The processor has Async memory interface(AMI), Enhanced Parallel Peripheral interface(EPPI).

If i am interfacing through Async Memory interface,

I think my address lines and data lines should be addressing some memory inside FPGA??(Is dat right)

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Yes. You probably want to create a bridge, where accesses from the blackfin AMI bus are translated into Altera Avalon transactions internal to the FPGA. Then you can construct the FPGA logic using Qsys or SOPC Builder.

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how can i connect four FPGAs??

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How fast will the bus be?

If you are clocking the interface at high frequency, then you do not want to connect the processor to all four FPGAs directly, since the PCB routing will be difficult. If you can afford to lose FPGA pins, then you can daisy-chain the buses, i.e., the processor connects to the first FPGA, the first FPGA connects to the second, etc. For example see the photo here:

http://www.ovro.caltech.edu/~dwh/carma_board/

The PowerPC connects to the first FPGA, and then the buses pass through each FPGA. The routing on the board is all short links.

Cheers,

Dave

I am actually using a high frequency design probably 600Mhz. I am taking a Chip select, R/W, PPI(Parallel Peripheral IF) lines( 8 data lines and a clk) to every FPGA of which PPI lines are common. I feel, taking PPI lines in common to all FPGA may create some issues ???

or else should i go for any alternatives??:confused:

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I am actually using a high frequency design probably 600Mhz.

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What do you mean by this comment? The Blackfin core may operate at 600MHz, but I highly doubt that the external bus will.

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I am taking a Chip select, R/W, PPI(Parallel Peripheral IF) lines( 8 data lines and a clk) to every FPGA of which PPI lines are common. I feel, taking PPI lines in common to all FPGA may create some issues ???

or else should i go for any alternatives??:confused:

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Using a common bus at high frequency might not work. You will have transmission line effects that result in poor signals. If you have to do it, then you need to simulate the PCB layout in hyperlynx or some other PCB signal integrity simulation software.

Please explain what you are trying to do, and your data rate requirements, and I'll have a look at the Blackfin data sheet in a little more detail.

Cheers,

Dave

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What do you mean by this comment? The Blackfin core may operate at 600MHz, but I highly doubt that the external bus will.

Using a common bus at high frequency might not work. You will have transmission line effects that result in poor signals. If you have to do it, then you need to simulate the PCB layout in hyperlynx or some other PCB signal integrity simulation software.

Please explain what you are trying to do, and your data rate requirements, and I'll have a look at the Blackfin data sheet in a little more detail.

Cheers,

Dave

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Hi Dave,

In my project I am goin to use four FPGAs. Each FPGA should be connected individually to the controller as per the requirements from the customers.

I need to download the code for FPGA from my controller. I thought it would be better to connect it with serial communication(Ease of use). So i used SPI bus to interface it individually.

But My boss feels parallel buses will be much more faster than serial bus. So he wants to test its functionality. The parallel bus supports a maximum frequency data-rate of 75 Mhz. With such high data rate common bus to all FPGAs may cause an issue.

My boss insists to use Enhanced parallel peripheral interface(EPPI) in ADSP BF548. Since i am a designer i want to know the Trade-offs in it and check its feasible usage.

Thanks and Regards,

Iyan

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In my project I am goin to use four FPGAs. Each FPGA should be connected individually to the controller as per the requirements from the customers.

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Its unlikely that the customer feels very strongly about how the connections are implemented. What the customer will really need to specify is whether the four FPGAs are individually re-configurable once the power is on. If all FPGAs power-up, and they are never re-configured, then the inter-connectivity of the FPGAs is of no consequence. As far as their software is concerned it will look like four individual locations in the Blackfin memory map.

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I need to download the code for FPGA from my controller. I thought it would be better to connect it with serial communication(Ease of use). So i used SPI bus to interface it individually.

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Download what code? FPGA re-configuration image? NIOS II processor image? Or are you just referring to reading/writing registers inside a programmed FPGA?

You cannot configure an FPGA using an SPI interface. That needs to be done via the FPGA programing pins.

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But My boss feels parallel buses will be much more faster than serial bus. So he wants to test its functionality. The parallel bus supports a maximum frequency data-rate of 75 Mhz. With such high data rate common bus to all FPGAs may cause an issue.

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Sure, but its not too hard to put fanout buffers, or a small Cyclone IV FPGA on the board for the purpose of acting as a system controller/bus bridge. If you are designing a board with four large FPGAs, then a $15 Cyclone IV would not add much to the price-tag, but would make life much easier.

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My boss insists to use Enhanced parallel peripheral interface(EPPI) in ADSP BF548. Since i am a designer i want to know the Trade-offs in it and check its feasible usage.

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At the moment, you have the design sequence backwards. What you need from the customer is:

1) Do the FPGAs need to be dynamically reconfigured? As a single block (all four at once), or individually?

That defines how you need to implement the configuration logic, and it defines how you need to implement the bus connectivity, eg., you cannot cascade the buses through FPGAs, if one can be reconfigured while the others are supposed to be alive.

2) What is the data bandwidth required between the FPGAs and the processor core? For example, if each FPGA is generating 10MB/s of data that you need to get into the Blackfin for processing, then that helps define which buses you can consider.

See if you can locate that information, or ask the customer to clarify their requirements. Post a response to this thread when you get it. Also post the FPGA part numbers.

Cheers,

Dave

Thnx

I ll post ASAP :)