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What do you mean by this comment? The Blackfin core may operate at 600MHz, but I highly doubt that the external bus will.
Using a common bus at high frequency might not work. You will have transmission line effects that result in poor signals. If you have to do it, then you need to simulate the PCB layout in hyperlynx or some other PCB signal integrity simulation software.
Please explain what you are trying to do, and your data rate requirements, and I'll have a look at the Blackfin data sheet in a little more detail.
Cheers,
Dave
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Hi Dave,
In my project I am goin to use four FPGAs. Each FPGA should be connected individually to the controller as per the requirements from the customers.
I need to download the code for FPGA from my controller. I thought it would be better to connect it with serial communication(Ease of use). So i used SPI bus to interface it individually.
But My boss feels parallel buses will be much more faster than serial bus. So he wants to test its functionality. The parallel bus supports a maximum frequency data-rate of 75 Mhz. With such high data rate common bus to all FPGAs may cause an issue.
My boss insists to use Enhanced parallel peripheral interface(EPPI) in ADSP BF548. Since i am a designer i want to know the Trade-offs in it and check its feasible usage.
Thanks and Regards,
Iyan
Honored Contributor
