Forum Discussion
Altera_Forum
Honored Contributor
13 years agoI am actually using a high frequency design probably 600Mhz. I am taking a Chip select, R/W, PPI(Parallel Peripheral IF) lines( 8 data lines and a clk) to every FPGA of which PPI lines are common. I feel, taking PPI lines in common to all FPGA may create some issues ???
or else should i go for any alternatives??:confused: