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I am actually using a high frequency design probably 600Mhz.
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What do you mean by this comment? The Blackfin core may operate at 600MHz, but I highly doubt that the external bus will.
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I am taking a Chip select, R/W, PPI(Parallel Peripheral IF) lines( 8 data lines and a clk) to every FPGA of which PPI lines are common. I feel, taking PPI lines in common to all FPGA may create some issues ???
or else should i go for any alternatives??:confused:
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Using a common bus at high frequency might not work. You will have transmission line effects that result in poor signals. If you have to do it, then you need to simulate the PCB layout in hyperlynx or some other PCB signal integrity simulation software.
Please explain what you are trying to do, and your data rate requirements, and I'll have a look at the Blackfin data sheet in a little more detail.
Cheers,
Dave
Honored Contributor
