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I am in need to interface four FPGAs to ADSP BF548 processor. what type of interface can i use??
The processor has Async memory interface(AMI), Enhanced Parallel Peripheral interface(EPPI).
If i am interfacing through Async Memory interface,
I think my address lines and data lines should be addressing some memory inside FPGA??(Is dat right)
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Yes. You probably want to create a bridge, where accesses from the blackfin AMI bus are translated into Altera Avalon transactions internal to the FPGA. Then you can construct the FPGA logic using Qsys or SOPC Builder.
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how can i connect four FPGAs??
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How fast will the bus be?
If you are clocking the interface at high frequency, then you do not want to connect the processor to all four FPGAs directly, since the PCB routing will be difficult. If you can afford to lose FPGA pins, then you can daisy-chain the buses, i.e., the processor connects to the first FPGA, the first FPGA connects to the second, etc. For example see the photo here:
http://www.ovro.caltech.edu/~dwh/carma_board/ The PowerPC connects to the first FPGA, and then the buses pass through each FPGA. The routing on the board is all short links.
Cheers,
Dave
Honored Contributor
