Navaneeth
New Contributor
3 years agoFPGA giving out partial answer
Hi,
We expect 9216 bytes of data as output from the FPGA, but we only get 1536 bytes of data. We have thoroughly verified our logic design using the ASE Simulator wherein we are correctly obtaining the required 9216 bytes of data as output without facing any issues.
Timing constraints are also met while synthesizing our design!
Please can you help by mentioning any guidance / how ASE and FPGA are different / what further factors should we consider which are causing points of difference b/w ASE and FPGA runs?
Thank you, anticipate reply/replies at the earliest.