Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

FPGA configuration time and PCIe secification

Has anyone used the PCIe interface of a Cyclone device while configuring it using the AS (active serial) scheme?

I'm using a Cyclone IV device (EP4CGX30F484) and planning to use its PCIe interface. I've read from the PCIe specification that the minimum time between the PC's power rails being stable and the PCIe PERST# signal being deactivated is T_PVPERL = 100 ms (acitvating and deactivating PERST# causes a reset of the PCIe interface and causes PCIe lanes to initialise). You get another 100 ms from receiving the PERST# signal before the sequence starts, so that's a total of 200 ms. The PCIe specification only states a minimum time between power being stable and sending the PERST# signal, so you could get a few seconds before you have to be ready, but I don't know if I can rely on this.

Using the active serial configuration scheme would take me 1.225 s, so it seems I have to use a different scheme, such as FPP. Altera recommend this in their application note AN529:

“For Cyclone IV GX devices to meet the PCIe 100 ms wake-up time requirement, you

must use PS configuration mode for the EP4CGX15, EP4CGX22, and EP4CGX30

(except for F484 package) devices and FPP configuration mode for the EP4CGX30

(only for F484 package), EP4CGX50, EP4CGX75, EP4CGX110, and EP4CGX150

devices.”

FPP is a pain because you need another chip to manage the configuration process and this chip (MAX II or a microprocessor) needs its own software.

So my question is: has anyone got the PCIe interface to work reliably while their configuration takes over 200 ms? I'd also like to hear if you haven't! Thanks.

54 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    maybe You have the formula to calculate configuration time for EP4CGX22 by MAX II from a single quad SPI flash ( N25Q128A13ESE40G ) in PS mode with PFL inside MAX II.

    --- Quote End ---

    To start with, simply determine if you can configure the device fast enough, i.e., 7,600,040/80ms = 95MHz. If you were going to use a MAX II to generate the DCLK signal, you would ideally use a clock at twice this frequency, and generate the 95MHz square wave as a divide-by-2. The TimeQuest analysis document was written to analyze the timing requirements of that case.

    You could conceivable clock the MAX II and DCLK from a common 95MHz signal, but you would have to then match the timing of the external 95MHz to the data generated by the MAX II. Its not impossible, but in my opinion, selecting a different device capable of using FPP mode is a much more reliably solution. I know, you might not have that option, I'm just providing my "process of elimination" for device selection and configuration.

    --- Quote Start ---

    PFL user guide ( p. 50 ) has the formula only for FPP.

    Or please tell what to modify in that formula so, that it can be used for PS instead of FPP.

    Thank You again!

    UPD.

    Formula is needed for PS mode with data compression.

    --- Quote End ---

    I'm not sure that any timing parameter provided for compression is reasonable. Is there documentation that shows the compression is linear with device density? i.e., that the bit-stream length for a half-full device is half as large as for a full device? If this documentation does not exist, then there is no way to predict that your configuration image is not going to "blow up", so that the configuration time exceeds the PCIe timing requirement.

    Basically you have to decide why you have to use an EP4CGX22 for an application targeting PCIe.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi everyone -

    So my understanding is that this discussion is to meet the fpga configuration/pcie enumeration timing spec when the fpga card and the host pc use the same power source.

    I am developing a card which is purely for learning purpose. So If I can power the fpga card separately and configure it well ahead of the pcie RST (i.e when PC enumerates) then i am good to go. Is that right ?

    Thanks

    JP
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi JP,

    --- Quote Start ---

    So my understanding is that this discussion is to meet the fpga configuration/pcie enumeration timing spec when the fpga card and the host pc use the same power source.

    I am developing a card which is purely for learning purpose. So If I can power the fpga card separately and configure it well ahead of the pcie RST (i.e when PC enumerates) then i am good to go. Is that right ?

    --- Quote End ---

    If your board is a PCIe end-point (peripheral), then that end-point must be ready to handle PCIe enumeration bus cycles shortly after reset, otherwise the BIOS will not enumerate the board.

    In some cases you can violate this requirement, and re-enumerate the PCIe bus at a later time. Linux supports this to some extent, but its a bit of a hack.

    In your case, you can pretty much do whatever you like. Worst-case you hit reset on the PC and force a warm reboot.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Hi JP,

    If your board is a PCIe end-point (peripheral), then that end-point must be ready to handle PCIe enumeration bus cycles shortly after reset, otherwise the BIOS will not enumerate the board.

    In some cases you can violate this requirement, and re-enumerate the PCIe bus at a later time. Linux supports this to some extent, but its a bit of a hack.

    In your case, you can pretty much do whatever you like. Worst-case you hit reset on the PC and force a warm reboot.

    Cheers,

    Dave

    --- Quote End ---

    Thanks Dave. A question off topic.

    I am working on a card using EP4CGX15 which will receive lvds data input and store it in PCs memory (thru PCIe link). Lets say to begin with I want to toggle an LED through PCIe.

    Can you suggest a very simple altera topology (building block) that I can work towards on the programming side. (Qsys etc)

    If I create a megacore function of PCIexpress and be able to talk to the Avalon ST interface through a logic block will that be enough ? Or DMA is needed for sure.

    Thanks

    JP