FPGA configuration time and PCIe secification

Hi everyone -

So my understanding is that this discussion is to meet the fpga configuration/pcie enumeration timing spec when the fpga card and the host pc use the same power source.

I am developing a card which is purely for learning purpose. So If I can power the fpga card separately and configure it well ahead of the pcie RST (i.e when PC enumerates) then i am good to go. Is that right ?

Thanks

JP